Holes and trench like patterns with a very high depth to width aspect ratio with micron or sub-micron openings have a number of applications in the manufacture of semiconductors. This description uses the term high aspect ratio holes to generically describe holes and trench like patterns that have a very high depth to width ratio of greater than 10 to 1. Various etching methods have been developed to generate such holes in silicon. The approaches use a lithographically defined mask pattern; wet chemical etch methods that take advantage of chemical selectivity along the crystal plane; and dry, plasma etch processes, which are done at low pressure to obtain a highly directional, anisotropic etch.
Very high aspect ratio holes have an application in semiconductor devices and in various Micro-Electro-Mechanical Structures (MEMS). In semiconductor DRAM devices trenches for high capacitance structures with low surface area having aspect ratios of 50:1 and higher are being investigated for advanced designs. For both semiconductor and MEMs devices, the need for subsequent patterning after making the very high aspect ratio holes usually requires a photolithographically defined mask pattern be made in a photosensitive polymer such as photoresist or photosensitive polyimide. In such a step, the high aspect ratio hole may be filled with the photosensitive polymer.
Following the processes that use the polymer mask pattern, the polymer mask must be stripped from the device. In some applications, it may be advantageous to remove the polymer material partially, to a controlled depth to allow processing the upper, exposed section of the hole while the remaining polymer protects the lower section in the hole. A DRAM capacitor application that uses such a capability to increase the capacitor's area is described in “New Materials Enhance Memory Performance” a review by J. Baliga, Semiconductor International, November 1999, p 79-90, see p. 80.
Particularly for semiconductor applications, an additional requirement of the polymer removal process is that the exposed surface of the device not be subject to electrical degradation. Types of degradation that can occur in plasma removal processes may come from energetic species as later described causing crystal damage or damage to a thin dielectric layer, partial removal of an underlying target layer, and heat damage to in-place layers.
Standard methods of removing photo-polymers involve a method referred to as “ashing” in which a low pressure electrical discharge generates a plasma that creates chemically reactive oxygen species that flow to the surface to strip off the polymer and convert the polymer to volatile oxide by-products (e.g., HOx, COx). For very high aspect ratio holes, the flux of active oxygen species, that reaches the bottom of the hole, decreases as the aspect ratio increases, with the result that the etch rate of the polymer slows dramatically. One means to avoid this is to use a High Density Plasma (HDP). In this process, an intense plasma is generated at a low pressure. This pressure is sufficiently low so that the path length between collisions of plasma generated reactive species is sufficiently long so that reactive ions can be injected into the hole by acceleration of an electric field set-up in a boundary layer “sheath” over the surface of the substrate. A problem with this HDP approach is that the energetic ion species can electrically degrade the device's electrical characteristics and a problem with all conventional plasma and wet chemical processes for holes having aspect ratios greater than 10:1, the etch rate significantly slows.
The prior art has used the concept of a long path length between collisions with other gas species to enable a reactive species to reach the bottom of a very high aspect ratio hole where the species can convert the polymer to volatile by-products.
Devices are now being fabricated for a growing number of applications that have dimensions in the micron and nanometer dimension range. For example, very small dimension sizes are utilized in advanced microelectronic IC logic and memory devices. A growing number of applications for miniaturized devices, referred to as Micro-Electro-Mechanical Structures (MEMS), such as micro-sensors and micro-positioners have been commercialized. Lithography developed for microelectronics production has readily been transferred to MEMS production, for defining a mask pattern from which the pattern can be transferred into a substrate material (e.g., silicon wafer) in a subsequent etch step. Any number of substrate materials may be used to make MEMS devices. Single crystal silicon is most commonly used for fabrication of MEMS as processes developed for manufacture of semiconductor devices can be transferred to MEMS production. Fabrication processes are now well established to form structures by etching very deep, straight walled structures into a substrate in which the orientation of the crystal structure is used to give a very high directionality to the etch.
However, limitations arise in fabricating free standing structures, multiple levels of such structures and in general not damaging relatively fragile, in-place device elements by other processes needed to complete fabrication of the integrated device. Methods to solve these limitations are needed to expand the application base while continuing to shrink the size of microstructures.
Conventional wet chemical and low pressure plasma removal processes designed for photoresist removal are unable to remove polymer from holes and trenches that have a very high depth to width aspect ration without damaging the surface of the device. Generally, conventional processes are unable to fully remove polymer from surfaces that have complex topologies and that may include over hanging device elements. Additionally, these processes cannot practically remove highly cross-linked polymers such as polyimide that can withstand elevated temperatures as needed for some manufacturing steps.
What is desired then is a method that will remove a polymer used to fabricate free standing microstructures for MEMS and semiconductor devices.
It is further desired to provide a method for removing a polymer from under device elements having relatively high depth to width aspect ratios and relatively high width to depth aspect ratios.
It is also desired to provide a method for removing a polymer used to fabricate free standing microstructures that will not damage the relatively fragile microstructures.
It is still further desired to provide a method for removing a polymer in a non-directional or fully isotropic manner.
It is further desired to provide a method for removing a polymer used to fabricate free standing microstructures that will remove the polymer at a relatively rapid rate.
It is yet further desires to provide a system and method for removing a polymer used to fabricate free standing microstructures that will remove highly cross-linked polymers, such as but not limited to polyimide.
It is also desired to provide a product having microstructures for MEMS and semiconductor devices that include relatively high depth to width aspect ratios and relatively high width to depth aspect ratios.